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Bay Microsystems Picks Tharas Systems' Hardware Accelerator To Enhance Its Verification Flow
SANTA CLARA, Calif., - NOVEMBER 12, 2001 - Tharas Systems, Inc., a provider of next-generation hardware acceleration solutions, announced today that Bay Microsystems, Inc., a Santa Clara, California based network processor vendor, has integrated Hammer™ hardware accelerator into its verification flow.
"We were looking for an acceleration solution that is easy to use, with compile times as fast as software simulators and debug features that do not dramatically slow down acceleration. Hammer offers a compelling performance and price advantage over competing solutions. Tharas partnered with us to integrate Hammer 8M into our verification flow in a very short time. We look forward to upgrading to their higher capacity system as soon as it is made available to us," said Tony Chiang, Vice President of Engineering at Bay Microsystems.
"The networking industry represents a major Verilog acceleration market for Tharas Systems. We are pleased that Bay Microsystems chose Hammer over other solutions. While the traditional verification approach of deploying software simulation for complex, multi-million gate chips and systems is running out of steam, FPGA-based acceleration solutions are notorious for very long compile times and a dramatic slowdown in accelerator performance when used in exhaustive debug mode. Hammer, with its breakthrough processor-based technology, offers a superior solution in terms of compile times, run times, debug features and ease of use. All this at a price less than one-half the competing FPGA-based systems," notes Prabhu Goel, Chairman & CEO of Tharas Systems.
Tharas Systems’ Hammer provides Verilog simulations with the fastest compile and run times, while at the same time offering ease of use and debug capabilities comparable to that of software simulators. Compile times are as fast as 4 minutes per Million RTL Gate-equivalent as compared to 8 hours per Million RTL Gate-equivalent for other FPGA-based systems. Run times range from 10 to 1000 times faster than software simulators. Hammer’s innovative hardware architecture includes a proprietary backplane that delivers more than 10 Gbps bandwidth, minimizing run time degradation during debug -- contrast this to dramatic loss of performance during run time of competing FPGA-based systems during debug.
Hammer works with existing RTL and gate-level verification environment. As a result, designers can continue to use their familiar verification software, including the most popular Verilog HDL-based simulators from Synopsys, Inc. (NASDAQ: SNPS) and Cadence Design Systems, Inc. (NYSE: CDN).
Hammer supports design sizes of up to 8Million Gates-equivalent RTL code, and can be combined with multiple memory models up to one Gigabyte in hardware. Hammer pricing varies between US$115,000 and US$280,000, based on system capacity.
About Tharas Systems
Tharas Systems develops and markets high performance verification systems to designers of complex integrated circuits and electronic systems. The Tharas solution leads to significant shortening of the verification cycle; the pay off is material reduction in time-to-market. Hammer™ offers a patented, next-generation hardware accelerator for Verilog simulations with the fastest compile times and run times, while at the same time offering ease of use and debugging capability comparable to that of software simulators. Increasing verification complexity is one of the main challenges of designing complex integrated circuits and systems today. Founded in 1998, Tharas is privately held and funded by venture capital and private investors from throughout the electronics industry. Corporate headquarters is located at 3016 Coronado Drive, Santa Clara, Calif., 95054. Visit Tharas Systems at www.tharas.com. For more specific product information, or call 1-408-855-3200.
About Bay Microsystems
Bay Microsystems Inc. is a privately held, fabless communication IC company focused on empowering carrier infrastructure OEMs in meeting the demanding requirements of the emerging optical internetworking market. Bay's innovative network processors combine scalability, intelligence processing and ultra-high performance in highly integrated single chip solutions. These processors deliver guaranteed sustained line rate operation of 10/20/40 Gbps regardless of traffic patterns and network services. Bay Microsystems enables system OEMs to deliver a whole new class of equipment to address the Optical Networking, Broadband Access, Datacom Infrastructure and Voice Gateway markets. Bay's highly experienced management and world-class engineering team have three generations of proven expertise in architecture, implementation, deployment, marketing and management of network processors. Bay Microsystems is a member of the Optical Internetworking Forum (OIF), MPLS, and ATM forums and actively participates in the IETF. For more information visit the website at www.baymicrosystems.com.
Hammer™ is a trademark of Tharas Systems Inc. Tharas acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
Editor Contacts:Tharas Systems
Rahm Shastry
(408) 855-3205
Bay Microsystems
Chuck Gershman
(408) 653-2181
Contact: Info at Bay